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8308915: RISC-V: Improve temporary vector register usage avoiding the use of v0 #14166
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👋 Welcome back dzhang! A progress list of the required criteria for merging this PR into |
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LGTM.
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Looks fine.
@DingliZhang This change now passes all automated pre-integration checks. ℹ️ This project also has non-automated pre-integration requirements. Please see the file CONTRIBUTING.md for details. After integration, the commit message for the final commit will be:
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@RealFYang @yhzhu20 Thanks for the review! |
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Going to push as commit e21f865.
Your commit was automatically rebased without conflicts. |
@RealFYang @DingliZhang Pushed as commit e21f865. 💡 You may see a message that your pull request was closed with unmerged commits. This can be safely ignored. |
We have some macro assembler functions that use v0 hardcoded as a temporary
register currently.
However, the mask value used to control execution of a masked vector
instruction is always supplied by vector register v0 in RVV1.0[1]. If v0 is
alive holding a mask value the the same time, this will cause spilling of
this vector register. So it is better to replace v0 with other vector registers to
improve code execution efficiency.
In addition, this pr also adds several missing spaces in the format of the
instructions, and fixes several pipeline classes.
[1] https://github.com/riscv/riscv-v-spec/blob/v1.0/v-spec.adoc
Testing:
QEMU w/ UseRVV:
Progress
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Using
git
Checkout this PR locally:
$ git fetch https://git.openjdk.org/jdk.git pull/14166/head:pull/14166
$ git checkout pull/14166
Update a local copy of the PR:
$ git checkout pull/14166
$ git pull https://git.openjdk.org/jdk.git pull/14166/head
Using Skara CLI tools
Checkout this PR locally:
$ git pr checkout 14166
View PR using the GUI difftool:
$ git pr show -t 14166
Using diff file
Download this PR as a diff file:
https://git.openjdk.org/jdk/pull/14166.diff
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